The present invention relates to a print data editing circuit in a serial printer.
In a printer having printing pins arranged in a print data, a data translation program is stored in a control ROM to offset timings of arrays of odd and even numbered printing pins according to the print data. A CPU controls a pin data output port of a print data editing circuit according to the control program so as to achieve proper printing.
FIG. 1 illustrates a pin data output port of a conventional serial printer having a 24-pin printing head. The output port includes registers 1 through 4 and 3-input OR gate 5. Each register consists of eight D flip-flops. The output terminal of OR gate 5 is connected to the clock input terminal of register 1. Write signals a, b, and c are supplied from a CPU (not shown) to OR gate 5. OR gate 5 supplies an ORed output signal to the clock input terminal of register 1 through one-bit signal line 10. Register 1 also receives 8-bit print data through data bus 6 from a print data memory (not shown) for storing print data. The 8-bit print data is latched by register 1 in response to the clock signal as the ORed output signal. Register 2 receives, through 4-bit signal line 11, 4-bit data (corresponding to odd pins) among the print data supplied through data bus 6. Register 2 also receives the 4-bit data (corresponding to odd pins) supplied from register 1 through 4-bit signal line 13. A total of 8-bit data is latched by register 2 in response to the clock signal as control signal a supplied through line 7. Register 3 latches 8-bit print data (a sum of 4-bit print data corresponding to even pins and 4-bit print data corresponding to odd pins) of register 1 in response to the clock signal as control signal b supplied through line 8.
A total of 4-bit data corresponding to even pins from register 1 and 4-bit data (corresponding to even pins) among the print data supplied through data bus 6 is supplied to register 4 in response to the clock signal as control signal c supplied through signal line 9.
The print data memory is addressed in units of 8 bits, as shown in FIG. 2. FIG. 3 shows a printing head when viewed from the platen. A distance between the even pins in one column and the odd pins in the other column is set to be 9 dots. Addresses m through m+29 are required for the print data memory to set data for these printing pins. Data setting starts with the odd pins in the other column but printing starts with the even pins in one column. Print data signals for pins P1, P3, P5, and P7 are respectively stored in odd bits at address m. Print data signals for pins P9, P11, P13, and P15 are respectively stored in odd bits at address m+1. Print data signals for pins P17, P19, P21, and P23 are respectively stored in odd bits at address m+2. Subsequently, print data signals for pins P2, P4, P6, and P8 are respectively stored in even bits at address m+27, print data signals for pins P10, P12, P14, and P16 are respectively stored in even bits at address m+28, and print data signals for pins P18, P20, P22, and P24 are respectively stored in even bits at address m+29. The print data signals in an order of addresses m, m+1, m+2, m+27, m+28, and m+29 are are supplied to the pin output port. Upon sending of the print data at address m or m+1 to the pin data output port, write signal a is also supplied thereto. Similarly, upon sending of the print data at address m+2 or m+27 to the pin data output port, write signal b is then supplied; and upon sending of the print data at address m+28 to the pin data output port, write signal c is sent thereto.
When print data at address m is sent to the pin data output port, odd bit print data at the same address is stored in register 1. When print data at address m+1 is sent to the pin data output port, a sum of odd bit print data at address m and odd bit print data at address m+1 is stored in register 2. Upon sending of print data at address m+2 to the pin data output port, print data at the same address is stored in register 1. Upon sending of print data at address m+27, a sum of odd bit print data at address m+2 and even bit print data at address m+27 is stored in register 3.
Upon sending of print data at address m+28 to the pin data output port, it is stored in register 1, and odd bit print data at address m+1 is stored in register 2. Upon sending of print data at address m+29 to the pin data output port, a sum of even bit print data at address m+28 and even bit print data at address m+29 is stored in register 4.
The odd bit print data and the even bit print data are stored in registers 2, 3, and 4. The even bit print data and the even bit print data are sent from registers 2, 3, and 4 to the corresponding drivers of the printing head pins, thereby performing printing.
A conventional print data editing circuit, however, requires three signal lines for sending the write signals, an OR gate for logically ORing the write signals, and four 8-bit registers, resulting in a complicated circuit arrangement.